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    HLS Academy offers users multiple entry points to find the information they need. One of these entry points is through our Topic collection. These topics address the critical issues designers need to understand to fully leverage the capabilities of High-Level Synthesis and Verification. While we continue to add new topics, users are encouraged to further refine collection information to meet their specific interests.

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Rajeev Sehgal

Rajeev Sehgal is the Product Line Director for Precision FPGA Synthesis product line since 2011. In this role he owns the complete product line including, R&D, Product Validation, Product Engineering, Marketing, Business development and Customer Support. Prior to that he was managing multiple R&D teams working on emulation runtime, HDL Link, emulation GUI, DFT Visualizer, Verification IPs, and Schematic Generator. He was instrumental in building strong R&D teams. He has been with IKOS, Mentor, Siemens EDA for over 25 years. Rajeev graduated from University of California, Irvine, with a Master of Science in Computer Engineering. He also graduated from Thapar Institute of Engineering and Technology, Patiala, with a Bachelors in Electronics Engineering.

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