|
Welcome to HLS Academy's Forum! :wave:
|
|
0
|
106
|
February 5, 2024
|
|
Hackathon questions and issues
|
|
34
|
192
|
November 4, 2025
|
|
RTL synthesis tools help reduce power by controlling the encoding of Finite State Machines. How is this handled in HLS?
|
|
1
|
18
|
August 7, 2025
|
|
What are the best practices for implementing efficient arithmetic operations in HLS?
|
|
1
|
21
|
August 7, 2025
|
|
How do HLS tools support and handle interfaces?
|
|
1
|
25
|
August 7, 2025
|
|
Since I design in C++ can I use the native datatypes for High Level Synthesis as well?
|
|
1
|
15
|
August 7, 2025
|
|
What is scope in design partitioning?
|
|
1
|
16
|
August 7, 2025
|
|
What are inline and block in hierarchies?
|
|
1
|
19
|
August 7, 2025
|
|
When is it not possible to pipeline with II=1?
|
|
1
|
24
|
August 7, 2025
|
|
How to handle memories when loops are unrolled?
|
|
1
|
19
|
August 7, 2025
|
|
What are the benefits of HLS?
|
|
1
|
24
|
August 7, 2025
|
|
How to add custom ASIC libraries in catapult tool ?
|
|
1
|
45
|
December 18, 2024
|
|
Partial unrolling vs. pipelining where II>1
|
|
0
|
101
|
September 16, 2024
|