From Simulink to High-Quality RTL using High-Level Synthesis — The Design Methodology

Nowadays many ASIC and FPGA design projects start with a Simulink reference model. The traditional path from an abstract floating-point Simulink model to high-quality RTL code is long and often requires multiple manual coding stages, several designers and multiple code bases to be maintained. This process can be simplified by using Catapult High-Level Synthesis (HLS) along with a sophisticated workflow.