HLS 101 - What Every RTL HW Design Team Needs to Know
High-Level Synthesis (HLS) extends hardware design, bridging RTL design/architecture and verification. This webinar introduces HLS, covering preparation of untimed algorithms, their transformation and PPA (power, performance, area) optimization by Catapult into RTL, plus verification methodology changes that complement HLS flows.
What you will learn:
- HLS vs. traditional design flow
- What does the use of HLS provide?
- The fundamentals of HLS
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