Verifying Hardware at the Source: Why a User-Visible HLS Scheduling Contract Matters in an Age of AI-Generated Design

This paper describes a methodology that shifts verification to the pre-HLS C++/SystemC model, enabled by a small, user-visible scheduling contract that constrains interface behavior while leaving block internals free to optimize. The result is reusable verification intent, performance-accurate source models, compositional reasoning, and—as AI increasingly authors hardware—trust based on checkable artifacts rather than authorship.