Telechips: RTL Hardware Design Acceleration for On-The-Fly Image (De-)Warper in Automotive SoC Using C++ HLS

We designed and verified the entire IP including line memory, position calculator, pixel interpolator, and BUS interface (AXI4) in C++. Meanwhile, HDL was only used for describing the register bank and RTL wrapper for the IP. We started designing from architecture search in a top-down manner and created C++ classes for each module we needed. Then we designed each module bottom-up, constructing a hierarchy of classes. Finally, we compared the result of our Catapult C++ design to that of reference Python code which performs fisheye dewarping using an OpenCV library. To verify the final RTL, we used our noble verification environment, TcSimGen, and compared the output images from C++ and RTL test benches to check if they match. Thanks to C++ simulation which runs much faster than RTL simulation (~100x), it took a total of 9 months to design and verify the million-gate dewarping IP by one hardware engineer. Furthermore, it was verified post-silicon in Dolphin 5, our automotive AP, and N-Dolphin, our AI accelerator.