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HLS 101

High-Level Synthesis (HLS) is a design methodology that raises the abstraction level above traditional RTL by starting with a C++ or SystemC description of a digital system. The methodology also incorporates trusted verification tools and techniques to ensure that the design is synthesizable and that both the original high-level description and resulting RTL meet the target specification. The resulting RTL can then be verified, synthesized into a netlist, and physically laid out using traditional tool flows.

For hardware design (HLS) and verification (High-Level Verification - HLV) there are considerable advantages to using this methodology to deliver high quality RTL, be it VHDL or Verilog. HLS is a critical approach to addressing the rising complexity of today’s digital systems. Designers can evaluate numerous architectural alternatives to find the best power, performance, and area in half the time with a fraction of the engineering resources of traditional RTL flows. At the same time, HLS enables orders of magnitude improvements in design verification and reliability.

Loop Unrolling

Loop unrolling is a fundamental optimization technique for driving parallelsim in High-Level Synthesis (HLS). By replicating loop bodies, loop unrolling enables multiple operations to execute concurrently, accelerating critical design paths. However, designers should recognize that inter-iteration dependencies can constrain full parallelism, even when a loop is partially or fully unrolled.

Pipelining

Pipelining means how often to start (the next) iteration of a loop or a function in High-Level Synthesis (HLS). It is defined with an Initiation Interval (II). The default II is generally 1, often implying continuous clock-by-clock throughput and minimal latency. However, in some cases, an Initiation Interval greater than one may be used, which can increase latency and is often due to resource constraints, feedback dependencies, or memory competition.

Hierarchy

Hierarchy is a fundamental concept in both Register Transfer Level (RTL) and High-Level Synthesis (HLS) for managing design complexity, promoting modular design, and enabling IP reuse. In SystemC, hierarchy is defined explicitly using SC_MODULE constructs that clearly specify interfaces, along with clock and reset signals. In C++-based HLS, hierarchy and parallelism are modeled implicitly and later transformed into an explicit RTL structure, ensuring accurate, efficient hardware implementation.

Design Partitioning

Design partitioning is a powerful technique that enables designers to manage complexity more effectively and optimize distinct elements of a system for improved performance and reuse. By logically grouping mutually exclusive functions or operators, partitioning allows better control over resource sharing and optimization strategies.

Partitions can be combinational, supporting simpler logic clusters, or sequential, incorporating pipelined datapath elements to meet higher frequency targets or accommodate a larger number of operators. Thoughtful design partitioning helps maintain clarity, scalability, and efficiency across complex hardware systems.

Data Types

Bit-accurate data types offer a reliable mechanism to model exact hardware bit-widths and arithmetic precision in High-Level Synthesis (HLS) workflows. These types range from simple signed and unsigned integer representations, familiar to RTL designers, to fixed point data types with support for rounding and saturation modes, and even fully IEEE-compliant floating point types with user-defined exponent and mantissa widths. This level of control ensures bit-exact behavior, maintaining alignment between C++/SystemC numerical models and the final RTL generated by the HLS tool.

Some organizations use proprietary or custom-developed bit-accurate types for modeling. However, two widely available open-source options are AC types and SystemC types they support robust C++/SystemC design styles and offer comprehensive integer and fixed point modeling capabilities. AC Types have become especially popular due to their support for unlimited bit-length, consistent simulation semantics, and faster execution performance in compiled environments.

Interfaces

Interfaces in High-Level Synthesis (HLS) are crucial components that define how a hardware module communicates with other modules or the external environment. They play a vital role in determining the overall performance and functionality of the synthesized hardware.

Interfaces in HLS can range from basic unsynchronized wires linked to Control/Status Registers, to more advanced streaming, SRAM, and bus-based interfaces. Effective data movement plays a crucial role in optimizing bandwidth and overall system-level performance. Common HLS interfaces often use channels or connections with clear ready/valid/data signaling, enabling structured communication and efficient design implementation.

Arithmetic Functions

Arithmetic functions are a vital part of High-Level Synthesis (HLS), especially in designs that involve intensive mathematical computations. Whether targeting FPGA or ASIC platforms, arithmetic operations are central across application domains. These arithmetic functions can be as simple as the basic operators such as adders, multipliers, dividers; to more complicated functions such as trigonometric functions, squares, roots, exponents, logarithms. On FPGAs, these are typically mapped to DSP blocks and LUTs, while in ASIC designs, they are implemented using standard cell libraries optimized for the target technology node.

Datapath

In hardware, an input data traverses through muxes, arithmetic and logic circuits to provide the output data. This path of traversal or this collection of functional units is called Datapath, and this represents the functional behavior of what the designer intended to do.

In High-Level Synthesis (HLS), the Datapath operations are initially allocated from the selected FPGA or ASIC design library and then scheduled based on the clock period, registering where required into different clock steps with the help of a Finite State Machine. Datapath contains information of data flow or in other words – “data dependencies”. The hardware datapath captures critical data dependencies, which must be managed to avoid feedback issues during RTL generation. Accurate clock scheduling and hardware optimization make the datapath one of the most essential elements in any HLS-driven digital design.

Control Logic and FSM

High-Level Synthesis (HLS) automatically generates control logic and finite state machines (FSM) to optimize digital circuit design. The control logic manages data movement, pipeline stages, and resource sharing, while the FSM handles state transitions and operation sequencing in the data path. This powerful combination streamlines hardware design by efficiently managing operations and dependencies. Through advanced techniques like loop unrolling and pipelining, HLS enables engineers to convert high-level algorithms into optimized hardware implementations, enhancing overall circuit performance and efficiency. The system effectively handles conditional statements and loop structures, making it essential for modern digital circuit optimization and hardware design workflows.

Memories

Types of Memories in High-Level Synthesis (HLS) include Single Port RAM, Read Only Memory (ROM), First In First Out (FIFO), and True Dual Port RAM. These storage components are mapped from arrays in HLS C++ based on their size and usage, implemented as block RAM, distributed RAM, registers, and FIFOs. The necessary addresses, data, and control signals needed to access the memories are automatically created. Several pre-built FPGA and ASIC memory libraries are included in HLS for the supported technologies, featuring user-defined latency to add register banks to the input and output of the memories and configurable Read/Write Resolutions where supported. In addition to these memory libraries, custom memory libraries can be generated using a Memory Generator in HLS, which allows users to read in VHDL or Verilog models of memory and generate vendor-specific custom memory libraries. This utility is particularly useful for creating ASIC memories from IP groups or foundries.

Channels & Bus Interfaces

In High-Level Synthesis (HLS), channels are used to model data streaming interfaces and simplify system design and synthesis. Channels serve as flexible, FIFO-based connections between blocks, supporting any data type and enabling reliable data transfer in the correct order. This ensures streaming behavior in hardware can be accurately modeled and synthesized. Channels also help manage mismatched data rates between blocks, and maintains consistency between simulation and synthesis. By enabling support for various bus protocols, channels provide bus interface behavior, allowing for streamlined integration of control signals, data, and synchronization in complex, hierarchical systems.

IP

High-Level Synthesis (HLS) IP cores are soft IP cores but in the form of a high level language instead of RTL languages. They are generally present as C/C++, SystemC.

Open-Source Foundation libraries for HLS

The High-Level Synthesis (HLS) Foundation Libraries represent a powerful open-source initiative implemented in standard C++, enabling precise bit-accurate hardware and software design. These comprehensive libraries serve as a catalyst for hardware acceleration, offering robust, synthesizable building blocks for both FPGA and ASIC implementations. The goal of these libraries is to create an open community for exchange of knowledge and IP for HLS that can be used to accelerate both research and design. These libraries are delivered as an open-source project on GitHub under the Apache 2.0 license and contributions are welcome. Whether you're working on academic research or industrial applications, these libraries provide the essential building blocks for efficient hardware design and implementation.

C++ Modeling

High Level Synthesis (HLS) designs leverage untimed C++ programming for efficient hardware modeling, offering streamlined coding practices and superior simulation performance. This approach enables developers to model hardware blocks through C++ classes, while managing design hierarchy and interconnections via class function calls. The implementation supports both fixed-point and floating-point datatypes, ensuring accurate modeling of numerical precision, saturation, and rounding operations. Comprehensive C++ libraries enhance HLS capabilities by providing ready-to-use components for mathematical operations, DSP functionalities, and various hardware-specific implementations, streamlining the hardware design workflow.

SystemC Modeling

Using SystemC to model High-Level Synthesis (HLS) designs enables a wide range of hardware design types to be modeled and efficiently verified before HLS. SystemC enables comprehensive hardware aspects to be modeled, including modules and module hierarchy, ports, signals, concurrent processes, reset signals, and precise timing control. All major HDL simulators support simulation of mixed testbench and design hierarchies that seamlessly integrate SystemC, SystemVerilog, and VHDL modules for complete design verification. Within SystemC HLS models, libraries such as MatchLib facilitate transaction interfaces and provide essential building block IP models. These models leverage both fixed-point and floating-point datatypes to accurately represent limited numerical precision, saturation, and rounding operations. The extensive C++ libraries for HLS empower designers to model complex math functions, DSP operations, and various hardware functionalities, making SystemC a powerful solution for modern hardware design workflows.

High-Level Verification (HLV)

High-Level Verification (HLV) is the application of known and trusted verification techniques to High Level Synthesis (HLS) design source. This advanced approach delivers remarkable performance gains, as simulations run at speeds up to 30, 100 or even up to 500x faster than comparable RTL simulations. HLV integrates seamlessly with established Design Verification (DV) methodologies, incorporating metrics-driven code coverage, functional coverage closure, and comprehensive test plan integration. The framework employs both dynamic and static verification techniques, including thorough lint checks and deep formal property verification, all executed before RTL generation. By implementing rigorous ASIC-quality signoff procedures at the HLS source level, HLV effectively prevents bug escapes into RTL while enabling efficient verification reuse during post-HLS RTL sign-off phases. This comprehensive verification strategy ensures robust design quality and accelerates the overall development cycle.

High-Level Static and Formal Verification

Sequential Logic Equivalence Checking (SLEC) and Formal Verification techniques provide robust validation for High-Level Synthesis (HLS) C-source designs. This comprehensive verification framework integrates advanced formal analysis methods. The C-Level verification suite combines simulation capabilities, coverage metrics, and formal property verification, mirroring established RTL design flows while operating at a higher abstraction level. Through formal proof techniques, designers can leverage assertions, coverage analysis, and reachability studies to validate design behavior systematically. The integration of formal methods with HLS enables automated proof of functional equivalence between high-level specifications and RTL implementations, while property checking ensures comprehensive verification closure. This powerful combination of static analysis and formal verification methodologies helps teams achieve thorough design validation and efficient coverage closure, significantly reducing verification cycles.

HLS FPGA

Achieving optimal algorithmic implementation using High-Level Synthesis (HLS) tools for FPGA development requires deep understanding of FPGA architecture and its capabilities. Modern FPGA devices offer sophisticated hardware resources that HLS tools can leverage, including specialized blocks like Block RAMs, DSP slices, and configurable shift registers. Leading FPGA vendors provide diverse configuration options through their HLS tools, supporting features such as true dual-port and simple dual-port memories, synchronous and asynchronous operational modes, and comprehensive arithmetic capabilities spanning both floating-point and fixed-point implementations. HLS FPGA tools enable efficient pipeline optimization through multiple register stages, allowing designers to fine-tune performance. When selecting an FPGA platform for HLS implementation, it's crucial to evaluate device-specific features, resource availability, and architectural advantages that align with design requirements. This strategic approach to FPGA selection and HLS tool utilization ensures optimal performance, resource utilization, and design efficiency in the final hardware implementation.

Processor Accelerators

High-Level Synthesis (HLS) enables developers to create domain-specific process accelerators to achieve higher performance and greater efficiency. As silicon scaling no longer delivers these gains, offloading complex algorithms from general-purpose processors to dedicated hardware accelerators improves performance, reduces power and cost, and optimizes area. This shift also can allow for the use of smaller, more efficient processors. HLS makes this transition fast and easy, while minimizing execution and scheduling risks.

MathWorks

MATLAB and Simulink integrate into the High-Level Synthesis (HLS) design flow to enable a seamless algorithm-to-RTL process with continuous verification. The workflow begins with algorithm development in MATLAB or Simulink, where floating-point models are created and validated. These models are then translated into C++ for High-Level Synthesis.

Crucially, the C++ models generated for HLS are folded back into the original MATLAB or Simulink testbenches, enabling system-level verification against the algorithmic reference. As the C++ model is refined for synthesis, it remains testable within the MathWorks environment using the High-Level Verification (HLV) framework. HLV provides model instrumentation and coverage analysis directly within the MATLAB testbench, helping improve DUT quality and the effectiveness of stimuli for subsequent RTL verification.

This integrated approach connects algorithm development, High-Level Synthesis, and RTL verification into a unified flow, ensuring consistent validation from model to implementation.

AI/ML Accelerators & Design

Machine learning algorithms are ideal for implementation using High-Level Synthesis (HLS), as they are both computationally complex and highly parallel. These workloads often underperform on general-purpose CPUs. HLS empowers designers to explore and optimize architectures for AI/ML accelerators, enabling the creation of custom solutions that can significantly outperform general-purpose accelerators like GPUs or TPUs by an order of magnitude or more.

Image/Video Processors & Design

The future of image and video processing is here, powering deepfakes, self-driving cars, and virtual reality. These innovations all stem from the fundamentals of digital signal processing. With modern AI now recognizing and generating images, the demand for high-performance image and video processors is growing. High-Level Synthesis (HLS) plays a key role in designing efficient, custom solutions for these applications. This page explores the basics of image and video processing and how HLS helps bring the next generation of visual technologies to life.