HLS 101 - Fundamentals of High-Level Synthesis

HLS extends hardware design, bridging RTL design/architecture and verification. This webinar introduces HLS, covering preparation of untimed algorithms, their transformation and PPA (power, performance, area) optimization by Catapult into RTL, plus verification methodology changes that complement HLS flows.

What you will learn:

• HLS vs. traditional design flow
• Modeling for HLS
• HLS transformations / optimizations, scheduling, analysis, verification & technology mapping