Optimizing SystemC/C++ Hardware Architectures Through High-Level Synthesis
Hardware architecture has a huge impact on RTL "quality of results" when deploying High-Level Synthesis (HLS). We will cover how to code different hardware architectures in C++ or SystemC to achieve optimal results in the output RTL.
What you will learn:
- Fundamental filter architectures and HLS coding style
- Windowing for efficient image processing
- Delay line implementation with a single-port RAMz
Full-access members only
Register your account to view Optimizing SystemC/C++ Hardware Architectures Through High-Level Synthesis
Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.