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    1. What is High-Level Synthesis

      High-Level Synthesis (HLS) is a design methodology that begins with a C++ or SystemC description of a digital system and then automatically translates and optimizes the design into an RTL implementation. The methodology also incorporates trusted verification tools and techniques to ensure that the design is synthesizable and that both the original high-level description and resulting RTL meet the target specification. The resulting RTL can then be verified, synthesized into a netlist, and physically laid out using traditional tool flows.

      HLS is a critical approach to addressing the rising complexity of today’s digital systems. Designers can evaluate numerous architectural alternatives to find the best power, performance, and area in half the time with a fraction of the engineering resources of traditional RTL flows. At the same time, HLS enables orders of magnitude improvements in design verification and reliability.

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    2. Who we are

      Welcome to the HLS Academy, a platform designed to help you develop the skills necessary to advance your organization's high-level design and synthesis processes. Our team comprises subject-matter experts in the industry dedicated to providing the necessary skills to mature an organization’s advanced HLS capabilities.

      We provide a practical approach to learning the core principles of using C++ and SystemC to describe your design and apply High-Level Synthesis and Verification tools to realize the full benefits of this advanced methodology.

      HLS Academy provides a wealth of resources, events, and tools to help design engineers stay up-to-date with the latest trends and techniques in the field.

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