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Wednesday, July 2, 2025 - Friday, October 31, 2025
Accelerating Inferencing Using HLS Hackathon
Energy efficiency is essential for edge devices, especially those powered by batteries or harvested energy, making low-power AI and machine learning inference a real challenge. In this hackathon focused on accelerating inferencing using HLS, your mission is to build a high-efficiency hardware accelerator that delivers accurate predictions with minimal energy per inference.
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Explore learning topics
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AI/ML Accelerators and Design
Machine learning algorithms are ideal for implementation in hardware using High Level Synthesis (HLS). They are computationally complex and highly parallel. They often perform poorly on general purpose CPUs. HLS enables designers to explore a wide range of architectures to achieve an optimal implementation. Bespoke AI accelerators can outperform general purpose accelerators, such as GPUs or TPUs by an order of magnitude or more. -
Arithmetic Functions
Arithmetic functions are a vital part of High-Level Synthesis (HLS), especially in designs that involve intensive mathematical computations. Whether targeting FPGA or ASIC platforms, arithmetic operations are central across application domains. These arithmetic functions can be as simple as the basic operators such as adders, multipliers, dividers; to more complicated functions such as trigonometric functions, squares, roots, exponents, logarithms. On FPGAs, these are typically mapped to DSP blocks and LUTs, while in ASIC designs, they are implemented using standard cell libraries optimized for the target technology node. -
C++ Modeling
Many High Level Synthesis (HLS) designs can be efficiently modeled using untimed C++, which features a simple coding style and very fast simulation performance. With this modeling approach, hardware blocks are modeled as C++ classes, and design hierarchy and block interconnect can be modeled using function calls between classes. Fixed-point and floating-point datatypes can be used to accurately model aspects such as limited numerical precision and saturation and rounding. C++ libraries for HLS enable blocks to model math functions, DSP functions, and more. -
Channels and Bus Interfaces
In High-Level Synthesis (HLS), channels are used to model data streaming interfaces and simplify system design and synthesis. Channels serve as flexible, FIFO-based connections between blocks, supporting any data type and enabling reliable data transfer in the correct order. This ensures streaming behavior in hardware can be accurately modeled and synthesized. Channels also help manage mismatched data rates between blocks and maintains consistency between simulation and synthesis. By enabling support for various bus protocols, channels provide bus interface behavior, allowing for streamlined integration of control signals, data, and synchronization in complex, hierarchical systems. -
Control Logic and FSM
High Level Synthesis (HLS) automatically infers control logic and finite state machine (FSM) for the scheduled operations. Control logic is responsible for the data movement in the data path. It manages pipeline stages, facilitates resource sharing, and decides the next state in the FSM. The FSM controls state transitions and sequencing of operations in the data path by generating control signals based on the scheduled design. Various FSM encoding techniques are available for optimization in HLS. -
Data Types
Bit-accurate data types offer a reliable mechanism to model exact hardware bit-widths and arithmetic precision in High-Level Synthesis (HLS) workflows. These types range from simple signed and unsigned integer representations, familiar to RTL designers, to fixed point data types with support for rounding and saturation modes, and even fully IEEE-compliant floating-point types with user-defined exponent and mantissa widths. This level of control ensures bit-exact behavior, maintaining alignment between C++/SystemC numerical models and the final RTL generated by the HLS tool.Some organizations use proprietary or custom-developed bit-accurate types for modeling. However, two widely available open-source options are AC types and SystemC types they support robust C++/SystemC design styles and offer comprehensive integer and fixed-point modeling capabilities. AC Types have become especially popular due to their support for unlimited bit-length, consistent simulation semantics, and faster execution performance in compiled environments. -
Datapath
In hardware, an input data traverses through muxes, arithmetic and logic circuits to provide the output data. This path of traversal or this collection of functional units is called Datapath, and this represents the functional behavior of what the designer intended to do.In High-Level Synthesis (HLS), the Datapath operations are initially allocated from the selected FPGA or ASIC design library and then scheduled based on the clock period, registering where required into different clock steps with the help of a Finite State Machine. Datapath contains information of data flow or in other words – “data dependencies”. The hardware datapath captures critical data dependencies, which must be managed to avoid feedback issues during RTL generation. Accurate clock scheduling and hardware optimization make the datapath one of the most essential elements in any HLS-driven digital design. -
Design Partitioning
Design partitioning is a powerful technique that enables designers to manage complexity more effectively and optimize distinct elements of a system for improved performance and reuse. By logically grouping mutually exclusive functions or operators, partitioning allows better control over resource sharing and optimization strategies.Partitions can be combinational, supporting simpler logic clusters, or sequential, incorporating pipelined datapath elements to meet higher frequency targets or accommodate a larger number of operators. Thoughtful design partitioning helps maintain clarity, scalability, and efficiency across complex hardware systems. -
HLS 101
High-Level Synthesis (HLS) is a design methodology that raises the abstraction level above traditional RTL by starting with a C++ or SystemC description of a digital system. The methodology also incorporates trusted verification tools and techniques to ensure that the design is synthesizable and that both the original high-level description and resulting RTL meet the target specification. The resulting RTL can then be verified, synthesized into a netlist, and physically laid out using traditional tool flows.For hardware design (HLS) and verification (High-Level Verification - HLV) there are considerable advantages to using this methodology to deliver high quality RTL, be it VHDL or Verilog. HLS is a critical approach to addressing the rising complexity of today’s digital systems. Designers can evaluate numerous architectural alternatives to find the best power, performance, and area in half the time with a fraction of the engineering resources of traditional RTL flows. At the same time, HLS enables orders of magnitude improvements in design verification and reliability. -
HLS FPGA
For an optimal implementation of algorithmic designs in an FPGA, it is important to understand the FPGA architecture and its functioning. Most FPGAs contain specialized resources such as RAMs, DSPs, shift registers – every vendor offers these blocks in multiple size configurations, features such as simple dual-port or true dual-port RAMs, synchronous versus asynchronous modes, floating-point versus fixed-point arithmetic operations, and various stages of pipeline registers. Therefore, it is critical to choose the right FPGA device with appropriate features that are best suited for your design. -
Hierarchy
Hierarchy is a fundamental concept in both Register Transfer Level (RTL) and High-Level Synthesis (HLS) for managing design complexity, promoting modular design, and enabling IP reuse. In SystemC, hierarchy is defined explicitly using SC_MODULE constructs that clearly specify interfaces, along with clock and reset signals. In C++-based HLS, hierarchy and parallelism are modeled implicitly and later transformed into an explicit RTL structure, ensuring accurate, efficient hardware implementation. -
High-Level Static and Formal Verification
Sequential Formal Verification techniques can be applied to C-source written for High Level Synthesis (HLS). A C-Level verification suite includes simulation, coverage metrics, and formal analysis very similar to direct RTL design flows. Assertions, covers and reachability analysis from C-based formal analysis all combine to give the designer and verifier feedback to close coverage and functionality efficiently. -
High-Level Verification
High-Level Verification (HLV) is the application of known and trusted verification techniques to High Level Synthesis (HLS) design source. HLV enables starting verification sooner, at the C++ and SystemC HLS level of abstraction, without waiting for RTL. As it operates on a higher level of abstraction, efficiencies are gained as simulations run at speeds up to 30, 100 or even up to 500x faster than comparable RTL simulations. A guiding principle of HLV is that is use methods that Design Verification (DV) teams are both already familiar with and also trust. Regarding dynamic verification, examples include metrics driven code and functional coverage closure and test plan integration. On the static and formal side, this means applying both static lint checks plus deep formal property checks on the HLS design source prior. All of this takes place prior to running HLS to produce RTL. While each team or product will likely have their own verification requirements, HLV must provide for rigorous and thorough techniques up to and including ASIC quality signoff on HLS design source. Another way to think of HLV is its goal is to ensure there are no bug escapes into RTL. With proper planning and forethought, HLV also facilitates re-use when it comes time to perform sign-off on the post-HLS RTL. -
IP
High-Level Synthesis (HLS) IP cores are soft IP cores but in the form of a high-level language instead of RTL languages. They are generally present as C/C++, SystemC. -
Image/Video Processors and Design
The future is now! Deep Fakes, Self-Driving Cars, Virtual Reality. What is this based on? What is next? Image and video processing is both an old and new industry. Modern technologies allow for AI to recognize objects and generate them. All these modern solutions start with the fundamentals of signal processing for digital images. How is an image recognized? How is an image processed? This page will cover the basics of image and video processing, how High-Level Synthesis can be used for these basics, and more. -
Interfaces
Interfaces in High-Level Synthesis (HLS) are crucial components that define how a hardware module communicates with other modules or the external environment. They play a vital role in determining the overall performance and functionality of the synthesized hardware.Interfaces in HLS can range from basic unsynchronized wires linked to Control/Status Registers, to more advanced streaming, SRAM, and bus-based interfaces. Effective data movement plays a crucial role in optimizing bandwidth and overall system-level performance. Common HLS interfaces often use channels or connections with clear ready/valid/data signaling, enabling structured communication and efficient design implementation. -
Loop Unrolling
Loop unrolling is a fundamental optimization technique for driving parallelsim in High-Level Synthesis (HLS). By replicating loop bodies, loop unrolling enables multiple operations to execute concurrently, accelerating critical design paths. However, designers should recognize that inter-iteration dependencies can constrain full parallelism, even when a loop is partially or fully unrolled. -
MathWorks
MATLAB and Simulink are integrated in High Level Synthesis (HLS) flow to enable seamless algorithm-to-RTL design process. The process begins with algorithm development in MATLAB/Simulink. The floating-point MATLAB or Simulink model is translated to C++ and instantiated in the original MATLAB or Simulink testbench for verification and validation purpose. The C++ model is further refined for High-Level synthesis and continuously validated in the MATLAB or Simulink testbench. The High-Level Verification framework provides HLS model instrumentation for coverage analysis that can be run inside the MATLAB testbench. The coverage information can be used to improve the DUT quality and the stimulus generator that can be used later for RTL verification. MATLAB/Simulink, High-Level Verification and Synthesis, and traditional RTL verification flow together enable seamless implementation and continuous verification flow from MATLAB/Simulink to RTL. -
Memories
High Level Synthesis (HLS) allows arrays to be mapped to different memory type resources such as block RAM, distributed RAM, registers, and FIFOs. The necessary addresses, data, and control signals needed to access the memories are automatically created. Several pre-built FPGA and ASIC memory libraries are included in HLS for the supported technologies. In addition to these existing libraries, custom libraries can also be created using Memory Generator which allows users to read in a VHDL or Verilog model of a memory and generate vendor specific custom memory libraries. -
Open-Source Foundation Libraries for HLS
The open-source foundational libraries for High Level Synthesis (HLS) implemented in standard C++ for bit-accurate hardware and software design. The goal of these libraries is to create an open community for exchange of knowledge and IP for HLS (High-Level Synthesis) that can be used to accelerate both research and design. The libraries are targeted to enable a faster path to hardware acceleration by providing easy-to-understand, high-quality fundamental building blocks that can be synthesized into both FPGA and ASIC. These libaries are delivered as an open-source project on GitHub under the Apache 2.0 license and contributions are welcome. -
Pipelining
Pipelining means how often to start (the next) iteration of a loop or a function in High-Level Synthesis (HLS). It is defined with an Initiation Interval (II). The default II is generally 1, often implying continuous clock-by-clock throughput and minimal latency. However, in some cases, an Initiation Interval greater than one may be used, which can increase latency and is often due to resource constraints, feedback dependencies, or memory competition. -
Processor Accelerators
High Level Synthesis (HLS) enables developers to create domain specific accelerators to deliver higher performance and greater efficiency. Designers can no longer rely on silicon scaling to deliver these improvements. By offloading computationally complex algorithms from the processor to hardware accelerators, performance, cost, power, and area can all be improved. Algorithms running on general purpose processors can be migrated to either co-processors or bus-based accelerators. This can enable the design to use a smaller, more efficient processor and increases parallelism. HLS makes the transition fast, easy, and minimizes execution and schedule risks. -
SystemC Modeling
Using SystemC to model High Level Synthesis (HLS) designs enables a wide range of hardware design types to be modeled and efficiently verified before HLS. SystemC enables hardware aspects to be modeled such as modules and module hierarchy, ports, signals, concurrent processes, reset signals, and time. All major HDL simulators support simulation of mixed testbench and design hierarchies that may contain SystemC, SystemVerilog, and VHDL modules. Within SystemC HLS models, libraries such as Matchlib can be used to enable transaction interfaces to be modeled and to provide building block IP models. SystemC HLS models can use fixed-point and floating-point datatypes to accurately model aspects such as limited numerical precision and saturation and rounding. C++ libraries for HLS enable blocks to model math functions, DSP functions, and more.
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NVIDIA's Use of Catapult HLS for Building ML Inference Accelerators
SystemC Modeling Nov 29, 2023 link
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What is High-Level Synthesis
Learn MoreHigh-Level Synthesis (HLS) is a design methodology that begins with a C++ or SystemC description of a digital system and then automatically translates and optimizes the design into an RTL implementation. The methodology also incorporates trusted verification tools and techniques to ensure that the design is synthesizable and that both the original high-level description and resulting RTL meet the target specification. The resulting RTL can then be verified, synthesized into a netlist, and physically laid out using traditional tool flows.
HLS is a critical approach to addressing the rising complexity of today’s digital systems. Designers can evaluate numerous architectural alternatives to find the best power, performance, and area in half the time with a fraction of the engineering resources of traditional RTL flows. At the same time, HLS enables orders of magnitude improvements in design verification and reliability.
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Who we are
Learn MoreWelcome to the HLS Academy, a platform designed to help you develop the skills necessary to advance your organization's high-level design and synthesis processes. Our team comprises subject-matter experts in the industry dedicated to providing the necessary skills to mature an organization’s advanced HLS capabilities.
We provide a practical approach to learning the core principles of using C++ and SystemC to describe your design and apply High-Level Synthesis and Verification tools to realize the full benefits of this advanced methodology.
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