AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS
Catapult HLS (High-Level Synthesis) and C-level design and verification are reducing entire project development times by half or more in today’s ASIC and FPGA designs. It is being used to create production-quality HW Accelerators for multiple applications such as 5G and Communication, Image and Video Processing, Automotive, and AI/ML much faster than hand-coded RTL with equivalent power, performance and area.
