| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| Welcome to HLS Academy's Forum! :wave: |
|
0 | 96 | February 5, 2024 |
| RTL synthesis tools help reduce power by controlling the encoding of Finite State Machines. How is this handled in HLS? |
|
1 | 4 | August 7, 2025 |
| What are the best practices for implementing efficient arithmetic operations in HLS? |
|
1 | 3 | August 7, 2025 |
| How do HLS tools support and handle interfaces? |
|
1 | 4 | August 7, 2025 |
| Since I design in C++ can I use the native datatypes for High Level Synthesis as well? |
|
1 | 3 | August 7, 2025 |
| What is scope in design partitioning? |
|
1 | 3 | August 7, 2025 |
| What are inline and block in hierarchies? |
|
1 | 3 | August 7, 2025 |
| When is it not possible to pipeline with II=1? |
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1 | 4 | August 7, 2025 |
| How to handle memories when loops are unrolled? |
|
1 | 3 | August 7, 2025 |
| What are the benefits of HLS? |
|
1 | 4 | August 7, 2025 |
| Hackathon questions and issues |
|
2 | 26 | July 11, 2025 |
| How to add custom ASIC libraries in catapult tool ? |
|
1 | 36 | December 18, 2024 |
| Partial unrolling vs. pipelining where II>1 |
|
0 | 83 | September 16, 2024 |