Topic	Replies	Views	Activity
Partial unrolling vs. pipelining where II>1 HLS Basics	0	86	September 16, 2024
Hackathon questions and issues Applications	6	43	September 13, 2025
Welcome to HLS Academy's Forum! :wave: Announcements	0	96	February 5, 2024
How to add custom ASIC libraries in catapult tool ? HLS Building Blocks & IP	1	38	December 18, 2024
How do HLS tools support and handle interfaces? HLS Basics Interfaces	1	8	August 7, 2025
What are the benefits of HLS? HLS Basics HLS-101	1	8	August 7, 2025
Since I design in C++ can I use the native datatypes for High Level Synthesis as well? HLS Basics Datatypes	1	7	August 7, 2025
What are inline and block in hierarchies? HLS Basics Hierarchy	1	7	August 7, 2025
When is it not possible to pipeline with II=1? HLS Basics Pipelining	1	7	August 7, 2025
RTL synthesis tools help reduce power by controlling the encoding of Finite State Machines. How is this handled in HLS? HLS Building Blocks & IP Control-Logic-and-FSM	1	6	August 7, 2025
What are the best practices for implementing efficient arithmetic operations in HLS? HLS Building Blocks & IP Arithmetic-Functions , Datapath , IP	1	6	August 7, 2025
What is scope in design partitioning? HLS Basics Design-Partitioning	1	6	August 7, 2025
How to handle memories when loops are unrolled? HLS Basics Loop-Unrolling	1	6	August 7, 2025