Control Logic & FSM

In HLS, control logic and FSMs play a fundamental role in converting algorithm descriptions into efficient hardware designs. It includes managing the sequencing of operations, handling dependencies, and coordinating data transfers in the hardware design.

Here’s how control logic and FSMs are implemented and optimized in HLS:

Conditional Statements

The HLS tool generates the necessary multiplexers and control signals that determine the execution path to handle branches of if-else conditions.

void comparison (int a, int b, int &c) {
if (a > b) {
c = a - b;
} else {
c = b - a;
}
}

For the above example, the control logic to select between the if-else conditions based on comparison is automatically generated by the tool.

Loops

HLS generates control logic to handle loop counters, termination conditions, and loop iterations.

Example:

void loops (int in[8], int &accum) {
    accum = 0;
    for (int i = 0; i < 8; i++) {
        accum += in[i];
    }
}

For the above example, HLS generated control logic will manage loop counter and accumulation in the order of sequence.

Loop Optimization Techniques

Loops in HLS can be optimized using techniques like loop unrolling and pipelining.

Loop Unrolling

Unrolling a loop creates multiple copies of the loop body resulting in parallel execution of iterations.

void loop_unroll (int in[8], int &accum) 
{
    accum = 0;
    #pragma hls_unroll 2
    for (int i = 0; i < 8; i++)
    {
        accum += in[i];
    }
}

For the above example, the unroll directive specifies HLS to parallelize the implementation by making two copies of the sequential loop body. HLS generated control logic manages the multiple operations simultaneously and handles data dependencies.

Loop Pipelining

Loop pipelining specifies how often to start the next iteration of a loop.

void loop_pipeline(int in[8], int &accum)
{
    accum = 0;
    #pragma hls_pipeline_init_interval 1
    for (int i = 0; i < 8; i++)
    {
        accum += in[i];
    }
} 

For the above example, the pipeline directive specifies HLS to overlap the loop execution every clock cycle, thereby improving overall design throughput. HLS generated control logic manages concurrency, data dependencies, handles memory read/write operations, manages memory access conflicts, and ensures data integrity.

Handling Data Dependency

HLS generates control logic to ensure data dependencies and avoid hazards.

void data_dependency (int a, int b, int &c, int &d) {
    int e = a + b;
    c = e; 
    d = e * 2; 
}

For the above example, the HLS generated control logic manages correct execution, ensuring that correct values are assigned to ‘c’ and ‘d’ without causing hazards.

Finite State Machines

Finite State Machines provide a structure representing control execution flow that transitions between states based on inputs and current state.

int state = 0;

void fsm (int input, int &output) {
    switch(state) {
        case 0:
            if (input) {
                state = 1;
            }
            break;
        case 1:
            state = 2;
            break;
        case 2:
            state = 0;
            break;
    }
}

For the above example, the control logic generated by the HLS tool will include the state transition logic and the control signals required for each state. HLS tool also provides FSM encoding directives for supported downstream RTL synthesis tools to potentially decrease power consumption by employing the following low-power state encoding methods:

• Binary encoding
• Gray code encoding
• One-hot encoding

To summarize, control logic manages the sequencing of operations, handling dependencies, coordinating data transfers, and optimizing parallel execution, while FSM provides a structured way to manage the control flow to meet specific application requirements. Understanding and leveraging these control logic and FSM mechanisms and their implementation allows for the creation of robust and efficient hardware that meets performance, area, and power requirements efficiently.