High-Level Verification

High-Level Verification (HLV) is the application of known and trusted verification techniques to High Level Synthesis (HLS) design source. This advanced approach delivers remarkable performance gains, as simulations run at speeds up to 30, 100 or even up to 500x faster than comparable RTL simulations. HLV integrates seamlessly with established Design Verification (DV) methodologies, incorporating metrics-driven code coverage, functional coverage closure, and comprehensive test plan integration. The framework employs both dynamic and static verification techniques, including thorough lint checks and deep formal property verification, all executed before RTL generation. By implementing rigorous ASIC-quality signoff procedures at the HLS source level, HLV effectively prevents bug escapes into RTL while enabling efficient verification reuse during post-HLS RTL sign-off phases. This comprehensive verification strategy ensures robust design quality and accelerates the overall development cycle.