High-Level Verification

High-Level Verification (HLV) is the application of known and trusted verification techniques to High Level Synthesis (HLS) design source. HLV enables starting verification sooner, at the C++ and SystemC HLS level of abstraction, without waiting for RTL. As it operates on a higher level of abstraction, efficiencies are gained as simulations run at speeds up to 30, 100 or even up to 500x faster than comparable RTL simulations. A guiding principle of HLV is that is use methods that Design Verification (DV) teams are both already familiar with and also trust. Regarding dynamic verification, examples include metrics driven code and functional coverage closure and test plan integration. On the static and formal side, this means applying both static lint checks plus deep formal property checks on the HLS design source prior. All of this takes place prior to running HLS to produce RTL. While each team or product will likely have their own verification requirements, HLV must provide for rigorous and thorough techniques up to and including ASIC quality signoff on HLS design source. Another way to think of HLV is its goal is to ensure there are no bug escapes into RTL. With proper planning and forethought, HLV also facilitates re-use when it comes time to perform sign-off on the post-HLS RTL.