SIEMENS HLS Academy

IP

IP cores in HLS are licensed reusable functional blocks of code designed in high-level language. They are licensed and sold to other vendors to be used as standalone designs or as block within their own design. Since they are re-used with any technology or library, ASIC or FPGA, they are designed to be as efficient as possible in terms of power, performance, and area. The IPs are usually verified behaviorally, formally and covered in both functional and code coverage.

The IP cores can be something as simple as a normalization function to something as complicated as an entire image processing algorithm. Designers can leverage the well designed and verified IP cores; along with the ease of designing with HLS they can reduce the time to market. This makes IP cores an important aspect of HLS designs.

Sivasankar Palaniappan

  1. IP Introduction

    IP Introduction

    IP cores are licensed reusable functional blocks of code which are licensed and sold to other vendors to be used as standalone designs or as block within their own design. Since they are re-used with any technology or library, ASIC or FPGA, they are designed to be as efficient as possible in terms of power, performance, and area. The IPs are usually verified behaviorally, formally and covered in both functional and code coverage.


    IP cores are of two categories:

    1. Hard IP Cores: These can be directly used in the final chip by the customer as they are in a layout format.
    2. Soft IP Cores: These are generally present as synthesizable RTL format such as verilog or VHDL. Customers can use it for their designs and customize it in the backend for placement and routing.

    HLS IP cores are soft IP cores but in the form of a high level language instead of RTL languages. They are generally present as C/C++, SystemC.

    Examples of HLS IPs

    HLS IPs are present in every domain or track of hardware designing. A few examples are:

    1. Communication domain
      1. Encoder: convolution, turbo, rice,
      2. Bit to Symbol mapping
      3. AES
    2. Digital Signal Processing domain
      1. FFT
      2. Interpolation
      3. Decimation (Frequency and Time)
      4. FIR Filter
      5. DCT
    3. Machine Learning Domain
      1. YoloTiny
      2. MNIST
      3. Conv2D
    4. Image Processing Domain
      1. Dithering
      2. Edge Detection
      3. Windowing
      4. Line Buffer
      5. Denoising
    5. AXI Interfaces
    6. Math
      1. Reciprocal
      2. Square
      3. Logarithm/power
      4. Matrix Operations
        1. Decomposition
        2. Inverse
        3. Determinant
        4. Multiplication

    Advantages of HLS IP

    1. Reuse: IPs can be reused in any design across different projects and teams. The source code can be dropped in to the customer’s design. Most of the IPs are templatized functions/source files in HLS and customers can call the functions or include the header files in the design making the use of IPs quite easy.
    2. Time to Market: IPs have already been designed to have the best possible area, performance and power. Hence the designers can plug it in, and customers do not need to worry much about optimization of the IP blocks. This saves up on a large amount of time which should help the user to market their chip to the market much faster.
    3. Verification: The IP blocks generally are verified in the following ways:
      This will help save time in having to verify these IP blocks individually and instead verification teams would just need to verify blocks with the IPs dropped in.
      1. gcc/g++ simulation
      2. Co-simulation with RTL
      3. Basic Code Coverage
      4. Basic Functional Coverage
      5. Equivalence Checking
    4. Cost Saving: Designing new blocks will need a large amount of resources in terms of software, systems as well as human hours. Usage of IP will help save time and cost for designing new blocks as they are designed to have the best possible PPA metrics and verified behaviorally and functionally as well. Reusability means they will not need to be designed afresh for each team/project and can be used again by modifying existing templatized parameters/switches.

    Conclusion

    Using HLS IPs can help designers market their chip quicker than having to design each block for every team/project. They are soft IPs where code is provided in High level languages such as C/C++, SystemC which can be used in their design by including header files and calling templatized functions. Designers do not need to worry much about performance metrics as generally HLS IPs are designed to provide the best performance, area, and power. Verification teams also do not need to worry about verifying these IPs as they are behaviorally and functionally pre-verified.

    HLS IPs can range from something as simple as a reciprocal function to complex design blocks such as protocols, image processing algorithms or machine learning algorithms. These IPs are licensed by manufacturers which the customers can buy and reuse for all their projects.

    We can conclude by saying that HLS IPs can help improve and quicken the chip design process by using pre-designed and pre-verified code blocks.