Making shift-left real: Why SystemC, MatchLib, and High-Level Synthesis are the right foundation for SoC design and verification in an age of AI

SoC teams try to find design and verification problems earlier, yet in most flows the first model that is both performance-accurate and authoritative is still the RTL, arrives late and simulates slowly. This paper argues SystemC models built with open-source MatchLib library and synthesized with Catapult HLS close the gap. Such models exist early, simulate 30x–100x faster than RTL, are accurate with respect to the final implementation, and are the actual source from which the RTL is generated.