HLS 101
High-Level Synthesis (HLS) typically uses C++ or SystemC to raise abstraction above that of RTL. For hardware design (HLS) and verification (HLV) there are considerable advantages to using this methodology to deliver high quality RTL, be it VHDL or Verilog.
It is important to understand that HLS still involves hardware design skills that the RTL designer will be experienced with. What you write in the source will materially impact the resulting RTL. This is especially true when it comes to memory architecture, interface bandwidth limits, and bit-accurate mathematical tradeoffs.
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HLS 101
High-Level Synthesis (HLS) is a design methodology that begins with a C++ or SystemC description of a digital system and then automatically translates and optimizes the design into an RTL implementation. The methodology also incorporates trusted verification tools and techniques to ensure that the design is synthesizable and that both the original high-level description and resulting RTL meet the target specification. The resulting RTL can then be verified, synthesized into a netlist, and physically laid out using traditional tool flows.
HLS is a critical approach to addressing the rising complexity of today’s digital systems. Designers can evaluate numerous architectural alternatives to find the best power, performance, and area in half the time with a fraction of the engineering resources of traditional RTL flows. At the same time, HLS enables orders of magnitude improvements in design verification and reliability.
HLS Basics Topics