HLS Hackathon

July 2, 2025 - October 31, 2025

Accelerating Inferencing Using HLS Hackathon

Learn More!

HLS & Lattice Semi Webinar

Tuesday, Oct 28th-9:00 AM PDT

Rapid Design Space Exploration of AI functions on Lattice FPGAs Using HLS

REGISTER NOW
SIEMENS HLS Academy

HLS 101

High-Level Synthesis (HLS) is a design methodology that raises the abstraction level above traditional Register-Transfer Level (RTL) by starting with a C++ or SystemC description of a digital system. The methodology also incorporates trusted verification tools and techniques to ensure that the design is synthesizable and that both the original high-level description and resulting RTL meet the target specification. The resulting RTL can then be verified, synthesized into a netlist, and physically laid out using traditional tool flows.
For hardware design, HLS and verification (High-Level Verification - HLV), there are considerable advantages to using this methodology to deliver high quality RTL, be it VHDL or Verilog. HLS is a critical approach to addressing the rising complexity of today’s digital systems. Designers can evaluate numerous architectural alternatives to find the best power, performance, and area in half the time with a fraction of the engineering resources of traditional RTL flows. At the same time, HLS enables orders of magnitude improvements in design verification and reliability.

Stuart Clubb

  1. Tracks

    • HLS 101 - Fundamentals of High-Level Synthesis

      HLS extends hardware design, bridging RTL design/architecture and verification. This webinar introduces HLS, covering preparation of untimed algorithms, their transformation and PPA (power, performance, area) optimization by Catapult into RTL, plus verification methodology changes that complement HLS flows.What you will learn:HLS vs. traditional design flow Modeling for HLSHLS transformations / optimizations, scheduling, analysis, verification & technology mapping

      Webinar Peter Frey

      • HLS 101

    • High-Level Synthesis - What, How and Why Now?

      HLS adoption is growing rapidly. This webinar covers HLS concepts, methods, use cases, and customer examples, trends and why companies use HLS for vision and deep learning.*Seminar Part 1 HLS for vision and Deep Learning Hardware Accelerators Seminar.What you will learn:Implement vision algorithms in FPGA/ASIC with PPA trade-offsAnalyze CNN inference for energy-efficient solutionsIntegrate HLS designs into a larger systemVerify designs in-system and deploy to FPGA prototypes

      Webinar Ellie Burns

      • HLS 101

    • HLS 101 - What Every RTL HW Design Team Needs to Know

      This webinar will provide an introduction to HLS and how an abstract, untimed algorithm representation is prepared for HLS, then transformed and optimized for power, performance and area by Catapult, resulting in high-quality RTL. Additionally, this webinar will introduce changes to the verification methodology that complement an HLS flow.What you will learn:HLS vs. traditional design flow What does the use of HLS provide?The fundamentals of HLS

      Webinar Stuart Clubb

      • HLS 101

    • High-Level Synthesis, It’s Still Hardware Design

      This white paper talks about who the key individuals are that need to be involved in a successful High-Level Synthesis (HLS) hardware design flow and the challenges of designing using HLS.

      PDF Michael Fingeroff

      • HLS 101

    • High-Level Synthesis (HLS): Status, Trends and Future Directions

      This paper touches base on the ways HLS is helping/shaping verification, power optimization, and design reuse. This transition is changing the way hardware design is taught and the research projects that are enabled by the availability of mature HLS tools.

      PDF

      • HLS 101

    • Move to a High-Level Synthesis (HLS) Flow to Remain Competitive

      Reliance on RTL design and verification lengthens schedules and reduces competitiveness. Successful companies remain agile, test many implementation strategies, adapt to last-minute specification changes, and stay on track. Their success is achieved with High-Level Synthesis (HLS) using C++ or SystemC.

      PDF

      • HLS 101

  2. Introduction

    High-Level Synthesis (HLS) is a process that automates the generation of production-quality Register-Transfer Level (RTL) implementations from high-level specifications. The high-level specifications here refer to languages such as C/C++ which are traditionally used for software design. However, using these high-level languages, high level synthesis tools help to generate RTL in Verilog, VHDL or SystemVerilog. For designs which are sub-system level or need throughput accurate designing, SystemC is used to provide the final RTL.

    Designing hardware in RTL has its advantages of providing the designer fine grained control over how exactly the hardware is to be designed. While HLS uses some level of abstraction due to the nature of the input languages, it does provide other benefits to make HLS a viable alternative option in the future for hardware design.

  3. Advantages of HLS

    1. Abstraction: Due to the abstract nature of C/C++, HLS provides the advantage of abstraction where it is quite easy and clean to create modules and describe the required hardware in the higher level to make it easier to design, debug and read.
    2. Accelerated Design Time: By automating the RTL implementation process, HLS greatly accelerates design time, allowing design teams to complete projects more quickly.
    3. Reduced Verification Effort: Just like how designing is easy with HLS, verification can also be done at the higher level. This shift-left verification is called HLV or High-Level Verification where verification is done in C/C++ in terms of gcc and then co-simulation is done by comparing if the generated RTL matches with the C/C++.
    4. Efficient Resource Allocation: This is a complex issue with a large number of possibilities if a hardware designer is handling parallelism in every location of a complex design. HLS tools handle this efficiently.
    5. Better design space exploration: HLS facilitates better design space exploration. Tools provide knobs or directives to change various aspects of the HLS design which does not need code modification. Lesser debug period makes this exploration faster and easier.
    6. Lesser Time to Market: More design space exploration, easier learning curve due to input language abstraction, less time for verification leads to faster time to market.
    7. Reduction of Cost: Easier design process and easier debug process lead to lesser resources being needed thereby reducing the overall cost.

  4. How does HLS work?

    1. How does HLS work?

      1. HLS builds Concurrent RTL modules from C++ Classes or Functions

      • C++ Class/function synthesized as a concurrent process
      • Clocked process in RTL

      The first table shows the function and the class in C++.

      void simple_function(<function interface variables>){ 

  <function body> 

} 

 

 

class simpleClass{ 

  … 

  public: 

  void simple_function(<function interface variables>){ 

    <function body> 

  } 

};

      The below table shows the RTL which is generated by the HLS tool:

      module simple_function ( <module ports> );  

  always@(posedge clk) 

    begin 

      <module body> 

    end 

endmodule

      2. HLS Adds Interface Protocols to Untimed C++

      • Adding an interface protocol to an untimed C++ design is known as “Interface Synthesis”
      • Port size and direction is inferred from the source
      • Source does not specify the protocol
      • Interface synthesis allows the protocol to be defined using the HLS tool

      3. HLS Infers Memories or Registers from C++ Arrays

      • Automatically mapped to ASIC or FPGA memories/registers
      • User control over memory mapping
      • Arrays on the design interface can be synthesized as memory interfaces

      4. HLS Explores Parallelism

      • Exploration done using loop transformations
      • Unrolling and pipelining

      5. HLS Automatically Analyzes C++ Designs

      • High-level synthesis analyzes the data dependencies between the various steps in the algorithm
      • Analysis leads to a Data Flow Graph (DFG) description

      6. HLS Performs Technology-Aware Optimizations

      • After DFG analysis each operation is mapped onto a hardware resource which is then used during scheduling
      • Resources are selected from a technology specific library

      7. HLS Automatically Closes Timing

      • High-level synthesis adds "time" to the design during the process known as "scheduling”
      • Scheduling automatically shares resources

      8. HLS Automatically Shares Resources

      • HLS shares resources
      • HLS shares registers

      9. HLS Builds Parallel Concurrent Processes from Sequential C++ Functions/Classes

      • Multi-block Design
        • Top-down or bottom-up
        • User specifies design blocks
      • Design-blocks/processes run in parallel

  5. Conclusion

    High level synthesis takes in input design in high level specification code such as C/C++, SystemC along with the target technology library to provide RTL. HLS provides abstraction to the user and helps reduce the overall code and time to market of designs. Verification is also easier with high level verification which is shift left verification making it a viable option for chip designers.

  6. HLS Basics Topics