HLS 101

HLS typically uses C++ or SystemC to raise abstraction above that of RTL. For hardware design (HLS) and verification (HLV) there are considerable advantages to using this methodology to deliver high quality RTL, be it VHDL or Verilog.

It is important to understand that HLS still involves hardware design skills that the RTL designer will be experienced with. What you write in the source will materially impact the resulting RTL. This is especially true when it comes to memory architecture, interface bandwidth limits, and bit-accurate mathematical tradeoffs.