Basic C++ and High-Level Synthesis
This track introduces engineers to C++, HLS and the use of HLS for hardware design.
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Sessions
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Loop Constraints for Synthesis
Explore some of the various looping and pipelining constraints which may be applied for RTL solution using HLS. -
Architectural Optimization: Folding Filter Coefficients For Symmetry
Further optimize the FIR filter design from Module 5 using architectural optimization, making use of the symmetry in the filter coefficients. -
Pipelining Constraints
Sample design used to explore functional and performance differences between pipelined vs. non-pipelined solutions.
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