Architectural Design and Synthesis of a Matrix Multiplication Block Using Catapult HLS and Matchlib

Whitepaper presents a HW design approach that enables rapid and precise block modeling at a higher level than RTL, followed by automatic synthesis to RTL using HLS. We demonstrate how fast and accurate architectural exploration leads to optimal designs, which can then be synthesized directly into RTL and integrated into the traditional RTL-to-silicon flow. The design process leverages Matchlib, an open-source library originally developed by NVIDIA Research and now supported in HLS tools.