HLS Academy Authors

Brucek Khailany joined NVIDIA in 2009 and currently leads the ASIC & VLSI Research group. During his time at NVIDIA, he has contributed to projects within research and product groups on topics spanning computer architecture, unit micro-architecture, and ASIC and VLSI design techniques. Dr. Khailany is also currently the Principal Investigator to a NVIDIA-led team under the DARPA CRAFT project researching high-productivity design methodology and design tools. Previously, Dr. Khailany was a Co-Founder and Principal Architect at Stream Processors, Inc. (SPI) where he led research and development activities related to highly-parallel programmable processor architectures. He received his Ph.D. and Masters in Electrical Engineering from Stanford University and received B.S.E. degrees in Electrical Engineering and Computer Engineering from the University of Michigan.

Cameron has joined Siemens in August 2023 through the Atlas New Graduate Program. Cameron graduated from Rochester Institute of Technology with a Masters Degree in Electrical Engineering focusing on Robotics, Embedded Systems, and Computer Vision. Cameron has held previous student roles at General Motors and Texas Instruments. Cameron is currently working primarily on marketing for low-level power estimation and analysis with the PowerPro team.

Dave Aerne is a Verification Technologist within the Calypto Systems Division, focusing on HLV (High-Level Verification) solutions. His particular areas of expertise are the UVM and Verification IP. Prior to joining the EDA industry, he gained over 18 years of SoC Design and Verification experience in various roles at semiconductor companies and fabless startups. Dave received a BSCompE from the University of Illinois at Urbana-Champaign and a MSCompE from National Technological University in Fort Collins, Colorado.

Petri Solanti is a senior application engineer at Siemens, with an HLS and low-power tools focus. He is a designer and application engineer with over 30 years of experience in Electronics System-Level design tools and methodologies. His areas of interest include design methodologies from algorithm to RTL, system analysis, model-based systems engineering, and HW/SW co-architecting. Prior to Siemens, Mr. Solanti held application engineer positions at Mentor Graphics, Cadence, CoWare, Synopsys and MathWorks. He received his MScEE degree from Tampere University of Technology, Finland and is currently pursuing a Ph.D in Electronics Engineering from Tampere University, Finland.

Rajeev Sehgal is the Product Line Director for Precision FPGA Synthesis product line since 2011. In this role he owns the complete product line including, R&D, Product Validation, Product Engineering, Marketing, Business development and Customer Support. Prior to that he was managing multiple R&D teams working on emulation runtime, HDL Link, emulation GUI, DFT Visualizer, Verification IPs, and Schematic Generator. He was instrumental in building strong R&D teams. He has been with IKOS, Mentor, Siemens EDA for over 25 years. Rajeev graduated from University of California, Irvine, with a Master of Science in Computer Engineering. He also graduated from Thapar Institute of Engineering and Technology, Patiala, with a Bachelors in Electronics Engineering.

Russell Klein is a program director with Siemens EDA. He also is an adjunct professor in the Electrical and Computer Engineering department at Portland state University. At Siemens, he works in the High-Level Synthesis (HLS) group, and is focused on algorithm acceleration using HLS to migrate functions from software running on embedded processors into bespoke accelerators.Mr. Klein has held a variety of engineering, marketing, and management roles at Siemens EDA, formerly Mentor Graphics, over 25 years. He has been awarded 6 patents related to hardware/software co-design and co-verification.

Sadhvi Praveen is High-Level Synthesis Technologist in the Catapult team, focusing on HLS for FPGA/ASIC. She has been with Siemens EDA for over 6 years, and has held various roles in pre-sales and technical marketing teams. She has a MS degree in Computer Engineering from Rochester Institute of Technology.

Sivasankar currently works as High Level Synthesis Technologist in the Marketing division of the Catapult team. He joined Siemens in July 2020 as an Associate Rotation Engineer and migrated to the new role a year later. Sivasankar has a MS in Electrical and Computer Engineering, focusing on Computer Engineering from University of California San Diego.

Stuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this new role, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics, Stuart held the position of Technical Marketing Engineer, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University, London, with a Bachelors of Science.

Stuart Swan is a Platform Architect in the Catapult team, focusing on SoC modeling for High-Level Synthesis. Prior to Siemens EDA, Stuart worked for Qualcomm and Cadence. Stuart is co-author of the first book on SystemC, "System Design with SystemC," and was the IEEE technical chairman of the 2005 SystemC LRM. He received his BSEE from Stanford University.